Location:
Search - clock recovery
Search list
Description: 简单的可配置dpll的VHDL代码。
用于时钟恢复后的相位抖动的滤波有很好的效果， 而且可以参数化配置pll的级数。-simple configurable dpll VHDL code. Clock Recovery for the jitter filtering is a very good result, but can pll configuration parameters of the series.
Platform: |
Size: 2037 |
Author: 陈德炜 |
Hits:
Description: 简单的可配置dpll的VHDL代码。
用于时钟恢复后的相位抖动的滤波有很好的效果， 而且可以参数化配置pll的级数。-simple configurable dpll VHDL code. Clock Recovery for the jitter filtering is a very good result, but can pll configuration parameters of the series.
Platform: |
Size: 2048 |
Author: 陈德炜 |
Hits:
Description: The code summerize how to calculate the jitter (RMS) with the incoming signals, such as optical communications and clock and date recovery circuit
Platform: |
Size: 881664 |
Author: marcus |
Hits:
Description: 基于FPGA的新型数据位同步时钟提取(CDR)实现方法-New FPGA-based data bit sync clock extraction (CDR) method
Platform: |
Size: 93184 |
Author: sam zeng |
Hits:
Description: 用于时钟恢复的全数字锁相环设计，可以去掉时钟的抖动。-Clock recovery for all-digital phase-locked loop design, the clock jitter can be removed.
Platform: |
Size: 1024 |
Author: BrivaMa |
Hits:
Description: 2MHz的数据时钟恢复电路，包括鉴相器、分频器及滤波器-2MHz data clock recovery circuit, including phase detector, divider and filter
Platform: |
Size: 2048 |
Author: Chen |
Hits:
Description: SerDes自顶向下的设计方法流程，包括接收机、发射机、均衡技术、时钟恢复技术-SerDes top-down design methodology process, including receivers, transmitters, equalization, clock recovery techniques
Platform: |
Size: 592896 |
Author: 周明珠 |
Hits:
Description: Clock data recovery .........good example
Platform: |
Size: 393216 |
Author: renu |
Hits:
Description: E1接收部分主要功能是实现从输入的差分线路数据中恢复出2.048M线路时钟并将数据解码输出。包括解码和线路时钟恢复两模块。-E1 to receive some of the major functions of the difference from the input data lines to recover a clock and data lines 2.048M decoder output. Including decoding and clock recovery circuits of two modules.
Platform: |
Size: 89088 |
Author: liusen |
Hits:
Description: DVB系统中基于QAM调制的时钟恢复算法的研究与实现,是研究数字接收机很好的参考资料-DVB System Based on QAM modulation clock recovery algorithm research and implementation, is to study a good reference for digital receiver
Platform: |
Size: 113664 |
Author: 晏子 |
Hits:
Description: 100以太网的时钟恢复电路，是涉及以太网的好资料，欢迎下载交流。-100 Ethernet clock recovery circuit, is related to Ethernet' s good information, please download the exchange.
Platform: |
Size: 201728 |
Author: 柳莺 |
Hits:
Description: 5B6B码是光纤数字通信系统中使用比较广泛的一种线路码型! 数据经过5B6B编码和并串转换后在光纤上传输，串行码序列中连续的比特0或比特1的长度不超过5，数据在0和1之间变换的密度很高,并具有直流平衡的特性，有利于接收电路和时钟恢复电路的设计。-5B6B code is used in fiber optic digital communication systems a more extensive line pattern! Data are 5B6B encoding and conversion, and string after the fiber transmission, serial code sequences in continuous bit 0 or bit 1 of the length of not more than 5, data between 0 and 1, the high density of transformation, and has the characteristics of DC balance, favorable reception circuit and clock recovery circuit.
Platform: |
Size: 3072 |
Author: 王彬 |
Hits:
Description: An All-Digital Phase-Locked Loop
(ADPLL)-Based Clock Recovery
Platform: |
Size: 394240 |
Author: malijun |
Hits:
Description: 摘 要:定时恢复是数字接收机中的关键技术,基于某特定LEO低轨卫星通信系统应用,重点研究了异步时钟采
样恢复法的工作原理,提出了一种改进的Gardner定时误差检测算法,给出了整个定时环路的具体实现方案,并针对其
性能进行了分析。仿真结果表明,在大多普勒加速度的卫星信道环境下,该方案能够满足系统设计的要求,且实现结
构简单、优化,可大幅降低算法复杂度,在较高信噪比的情况下,具有更加优化的性能。
-Abstract: The timing recovery is a key technology in the digital receiver, based on a particular application of LEO LEO satellite communication system, focus on the asynchronous sampling clock recovery method works, a modified Gardner timing error detection algorithm, given a concrete realization of the regular loop programs, and analyzed for its performance. Simulation results show that the acceleration of the satellite channels in large Doppler environment, the program can meet the requirements of system design and realization of simple structure, optimization, can significantly reduce the complexity of the algorithm, in the case of high SNR, with more optimized performance.
Platform: |
Size: 407552 |
Author: longx |
Hits:
Description: Jitter and clock recovery for periodic traffic in broadband packet networks
Platform: |
Size: 858112 |
Author: harsh |
Hits:
Description: white paper on Jitter and clock recovery for periodic traffic in broadband packet networks
Platform: |
Size: 173056 |
Author: harsh |
Hits:
Description: Clock recovery in TDM networks
Platform: |
Size: 478208 |
Author: vijay |
Hits:
Description: FPGA的5B6B编译码器的设计代码可以编译而且有波形图 -5B6B code is used in fiber optic digital communication systems a more extensive line pattern! Data are 5B6B encoding and conversion, and string after the fiber transmission, serial code sequences in continuous bit 0 or bit 1 of the length of not more than 5, data between 0 and 1, the high density of transformation, and has the characteristics of DC balance, favorable reception circuit and clock recovery circuit.
Platform: |
Size: 617472 |
Author: 邓小虎 |
Hits:
Description: 自己写的时钟提取逻辑。用于时钟恢复电路。-Write your own clock extraction logic. For the clock recovery circuit.
Platform: |
Size: 2048 |
Author: MML |
Hits:
Description: We propose a digital clock recovery algorithm and demonstrate its tolerance to at least 5GHz laser
frequency mismatch in a 43Gb/s DP-RZ-QPSK receiver after 1200km transmission.- We propose a digital clock recovery algorithm and demonstrate its tolerance to at least 5GHz laser
frequency mismatch in a 43Gb/s DP-RZ-QPSK receiver after 1200km transmission.
Platform: |
Size: 573440 |
Author: hamed |
Hits: